Power Electronics continues to be a critical aspect of connecting solar PV to the grid, and NCPRE continues to work on this. Gate voltage variation has the potential to be an effective method for Active Thermal Control (ATC) by manipulation of power loss in the Power Semiconductor Device (PSD). However, gate voltage variation in the ohmic region of static I-V characteristics does not change the power loss in PSD significantly. To address this challenge, this article discusses an ATC technique based on gate voltage variation in the saturation region of PSD. With the proposed controller, a wide range of power loss manipulation is achieved. Moreover, it avoids false triggering of desaturation protection through a suitable selection of gate voltage. The relationship between gate voltage and power loss in PSD is derived and found to be nonlinear in nature. The proposed controller compensates for this nonlinearity to achieve smooth control over the power loss in PSD. The proposed controller for temperature swing reduction is delineated along with generic guidelines for controller parameter selection. The control loop is linearized by using the aforementioned sensitivity analysis. The power loss in the PSD and its commutation process under different gate voltages are experimentally validated. At rated load, the power loss can be increased up to five times by using the proposed gate-voltage manipulation. This shows that the proposed approach achieves a large variation in the power loss of PSD without false triggering of desaturation protection. Compared to the conventional controller for the selected solar mission profile, the proposed controller reduces the temperature swing of up to 15.3 °C, which results in an increment in a lifetime by up to 43%. This work was done by NCPRE PhD student Abhishek Chanekar under the guidance of Prof. Sandeep Anand. A journal paper based on this work was published in IEEE Transactions on Power Electronics.